| 发明名称 |
SENSE AMPLIFIER OFFSET VOLTAGE REDUCTION |
| 摘要 |
A circuit includes a plurality of transistors responsive to a plurality of latches that store a test code. The circuit further includes a first bit line coupled to a data cell and coupled to a sense amplifier. The circuit also includes a second bit line coupled to a reference cell and coupled to the sense amplifier. A current from a set of the plurality of transistors is applied to the data cell via the first bit line. The set of the plurality of transistors is determined based on the test code. The circuit also includes a test mode reference circuit coupled to the first bit line and to the second bit line. |
| 申请公布号 |
US2015022264(A1) |
申请公布日期 |
2015.01.22 |
| 申请号 |
US201313947144 |
申请日期 |
2013.07.22 |
| 申请人 |
QUALCOMM Incorporated |
发明人 |
Kim Jung Pill;Kim Taehyun;Kim Sungryul;Kim Daeik D. |
| 分类号 |
G01R31/28;H03F1/00 |
主分类号 |
G01R31/28 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A circuit comprising:
a plurality of transistors responsive to a plurality of latches that store a test code; a first bit line coupled to a data cell and coupled to a sense amplifier; a second bit line coupled to a reference cell and coupled to the sense amplifier,
wherein a current from a set of the plurality of transistors is applied to the data cell via the first bit line, and wherein the set of the plurality of transistors is determined based on the test code; and a test mode reference circuit coupled to the first bit line and to the second bit line. |
| 地址 |
San Diego CA US |
