发明名称 Clock network architecture
摘要 An apparatus includes an integrated circuit with a clock network in an array of circuit blocks. The clock network includes routing tracks, distribution spines, and clock leaves. The routing tracks and the distribution spines are bidirectional.
申请公布号 US8937491(B2) 申请公布日期 2015.01.20
申请号 US201213677971 申请日期 2012.11.15
申请人 Xilinx, Inc. 发明人 Gaide Brian C.;Young Steven P.;Bauer Trevor J.;Ondris Robert M.;Gaitonde Dinesh D.
分类号 H03K19/177;H03K5/12;G06F1/04;H03K19/096;G06F1/10;G06F17/50 主分类号 H03K19/177
代理机构 代理人 Webostad W. Eric
主权项 1. An apparatus, comprising: an integrated circuit having a clock network in an array of circuit blocks; wherein the clock network includes routing tracks, distribution spines, and clock leaves; wherein a set of the leaves is coupled to a horizontal distribution spine of the distribution spines within a circuit block of the circuit blocks for providing a clock signal from the horizontal distribution spine to the set of the leaves; wherein an interconnect tile is configured for local gating for providing the clock signal to the set of the leaves without going through the horizontal distribution spine; and wherein the routing tracks and the distribution spines are bidirectional.
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