Timing driven routing for noise reduction in integrated circuit design

摘要

A mechanism is provided in a data processing system for timing-driven routing for noise reduction in integrated circuit design. Responsive to performing timing driving routing on an integrated circuit design, the mechanism identifies a set of noise-critical nets in the integrated circuit design. The mechanism performs timing driven routing on the integrated circuit design with noise constraints based on the set of noise-critical nets.

主权项

1. A method, executed in a data processing system, for timing-driven routing for noise reduction in an integrated circuit design, the method comprising:
responsive to performing a timing driven routing on an integrated circuit design, identifying a first set of noise-critical nets in the integrated circuit design based on the timing driven routing; performing an iterative routing on the integrated circuit design comprising:
iteratively performing a global routing and track assignment and a coupling timing on the integrated circuit design and, in response, identifying a second set of noise-critical nets in the integrated circuit design until the second set of noise-critical nets converges;performing a detail routing on the integrated circuit design with noise constraints and regular constraints;performing the coupling timing on the integrated circuit design to form a modified integrated circuit design; andidentifying a third set of noise-critical nets in the integrated circuit design; and responsive to determining that the third set of noise-critical nets and the second set of noise critical nets are equivalent, outputting the modified integrated circuit design.