Semiconductor device having counter circuit

摘要

A semiconductor device is disclosed which comprises a clock generating circuit generating first and second divided clocks by dividing an input clock by first and second division number, respectively, and a counter circuit including a shift register having a plurality of stages that sequentially shifts an input signal and outputs an output signal delayed based on setting information. The counter circuit individually controls operation timings of the stages of the shift register by selectively supplying either of the first and second divided clocks to each stage of the shift register, and either of signals from the stages of the shift register is extracted and outputted as the output signal.

主权项

1. A semiconductor device comprising:
a clock generating circuit capable of generating a first divided clock including a first phase by dividing an input clock by a first division number and a second divided clock including a second phase by dividing the input clock by a second division number, respectively, based on setting information; and a counter circuit including a shift register which includes a plurality of stages that sequentially shifts an input signal and outputs an output signal delayed based on the setting information, wherein the counter circuit is capable of individually controlling operation timings of respective stages of the shift register by selectively supplying either of the first and second divided clocks to the stages of the shift register and is capable of extracting either of signals outputted from the stages of the shift register to output it as the output signal, based on the setting information.