发明名称 |
Memory device and fabricating method thereof |
摘要 |
The present disclosure provides a memory device and a fabricating method thereof. The memory device includes a substrate including a first metal layer formed therein, the first metal layer having at least a first surface with at least a first exposed portion of the first surface exposed at a lateral surface of the substrate, at least a first semiconductor chip formed on a top surface of the substrate, and a second metal layer surrounding the first semiconductor chip and extending to lateral surfaces of the substrate, at least a first portion of the second metal layer contacting the exposed surface of the first metal layer. |
申请公布号 |
US8937370(B2) |
申请公布日期 |
2015.01.20 |
申请号 |
US201213430160 |
申请日期 |
2012.03.26 |
申请人 |
Samsung Electronics Co., Ltd. |
发明人 |
Song In-Sang;Song Sang-Sub |
分类号 |
H01L23/552;H01L23/00;H01L25/065;H01L23/498;H01L23/31;H01L21/56 |
主分类号 |
H01L23/552 |
代理机构 |
Muir Patent Consulting, PLLC |
代理人 |
Muir Patent Consulting, PLLC |
主权项 |
1. A semiconductor device comprising:
a substrate including a ground layer formed therein, the ground layer having at least a first surface with at least a first exposed portion of the first surface exposed at a lateral surface of the substrate; a plurality of first interconnections formed above the ground layer and spaced apart from the ground layer; a plurality of second interconnections formed below the ground layer and spaced apart from the ground layer; a plurality of conductive vias connecting respective first interconnections with respective second interconnections; at least a first semiconductor chip formed on a top surface of the substrate; a wire bonding connecting the first interconnections an the first semiconductor chip: a molding member disposed on the top surface of the substrate and configured to mold the semiconductor chip; and a shielding layer surrounding the molding member and extending to lateral surfaces of the substrate, at least a portion of the shielding layer contacting the exposed portion of the ground layer, wherein the ground layer has a plate-like shape extending laterally through the entire subtrate, werein at least a portion of the ground layer extends beneath an entire length of the semiconductor chip, and werein the ground layer includes a plurality of holes through which the plurality of conductive vias pass, and each conductive via is insulated from the ground layer by an instilation layer. |
地址 |
Yeongtong-gu, Suwon-si, Gyeonggi-do KR |