| 摘要 |
PURPOSE:To suppress that a power noise is transmitted to a power supplying path of an input buffer by providing all or one part of the power supplying path to a data output buffer independently of path to the other internal circuit. CONSTITUTION:Supplied X address signals AX0-AXi are signals of a TTL level, an initial inverter V1 of unit X address buffer UXB0-UXBi has a deviating logical threshold level suitable for the TTL level by changing conductance of a MOSFET P1 and N1. On the other hand, power voltage for operation of a third and fourth step inverters V3, V4 constituting the buffers UXB0-UXBi are the same power voltage VCC2, ground potential VSS2 as the other internal circuits except a data output buffer, but power voltage of inverters V1, V2 are independent voltage VCC3, VSS3. Therefore, the compression and malfunction of noise margin of the X address buffer caused by a power noise when an unit data output buffer becomes a simultaneous operation state can be prevented. |
