50 GB/S ETHERNET USING SERIALIZER/DESERIALIZER LANES

摘要

Systems, devices, and methods of implementing 50 Gb/s Ethernet using serializer/deserializer lanes are disclosed. One such device includes circuitry operable to provide a media access control (MAC) interface. The MAC interface is associated with a port having a 50 Gb/s link rate. The device also includes circuitry operable to generate Ethernet frames from data received at the MAC interface and circuitry operable to distribute the Ethernet frames across a group of serial/deserializer (SERDES) lanes associated with the port, the group having size N. The device also includes circuitry operable to transmit the distributed Ethernet frames on each of the SERDES lanes at a 50/N Gb/s rate.

主权项

1. A device comprising:
circuitry operable to provide a media access control (MAC) interface associated with a port having a 50 Gb/s link rate; circuitry operable to generate Ethernet frames from data received at the MAC interface; circuitry operable to distribute the Ethernet frames across a group of one or more serializer/deserializer (SERDES) lanes associated with the port, the group having a size N; and circuitry operable to transmit the distributed Ethernet frames on each of the SERDES lanes at a 50/N Gb/s rate.