发明名称 FULL ADDER CIRCUIT
摘要 A full adder circuit includes a first logical operation unit suitable for outputting an inverse of the second input signal and a first output signal corresponding to either a second input signal or the inverse of the second input signal in response to a first input signal, a second logical operation unit suitable for outputting an inverse of the first output signal and a sum signal corresponding to either the first output signal or the inverse of the first output signal in response to a carry input signal, and a third logical operation unit suitable for outputting a carry output signal in response to the inverse of the second input signal, the first output signal, the inverse of the first output signal, and the sum signal.
申请公布号 US2015019610(A1) 申请公布日期 2015.01.15
申请号 US201314085396 申请日期 2013.11.20
申请人 SK hynix Inc. 发明人 KIM Chang-Hyun
分类号 G06F7/501 主分类号 G06F7/501
代理机构 代理人
主权项 1. A full adder circuit, comprising: a first logical operation unit suitable for outputting an inverse of the second input signal and a first output signal corresponding to either a second input signal or the inverse of the second input signal in response to a first input signal; a second logical operation unit suitable for outputting an inverse of the first output signal and a sum signal corresponding to either the first output signal or the inverse of the first output signal in response to a carry input signal; and a third logical operation unit suitable for outputting a carry output signal in response to the inverse of the second input signal, the first output signal, the inverse of the first output signal, and the sum signal.
地址 Gyeonggi-do KR