发明名称 SOLDER FLOW IMPEDING FEATURE ON A LEAD FRAME
摘要 One embodiment is directed towards a packaged chip including a lead frame. At least one chip is mounted on the lead frame. At least one edge the lead frame has a solder flow impeding feature located thereon. The solder flow impeding feature includes an integral portion of the lead frame that extends in a first projection outward at an edge of the lead frame and parallel to an external surface of the lead frame. An internal surface of the first projection is aligned with an internal surface of the main portion of the lead frame. The solder flow impeding feature also includes a second projection that extends from an external side of the first projection in a direction generally perpendicular to the first projection.
申请公布号 US2015014835(A1) 申请公布日期 2015.01.15
申请号 US201414503620 申请日期 2014.10.01
申请人 INTERSIL AMERICAS LLC 发明人 Cruz Randolph;Carpenter, JR. Loyde Milton
分类号 H01L23/495 主分类号 H01L23/495
代理机构 代理人
主权项 1. A packaged chip comprising: a lead frame having a plurality of sections of conductive material, the plurality of sections including at least one floating section that does not abut against an edge of the lead frame, each section of the lead frame having a plurality of edges; at least one chip mounted on a section of the lead frame; wherein at least one of the sections includes an edge having a solder flow impeding feature located thereon, the solder flow impeding feature including an integral portion of the section of the lead frame that extends in a first projection outward at an edge of the section and parallel to an external surface of the section, wherein an internal surface of the first projection is aligned with an internal surface of the main portion of the at least one section, the solder flow impeding feature also including a second projection that extends from an external side of the first projection in a direction generally perpendicular to the first projection.
地址 Milpitas CA US