SEMICONDUCTOR MEMORY DEVICE HAVING IMPROVED FUSE SENSING RELIABILITY IN SLOW POWER UP OPERATION AND THEREFORE METHOD OF FUSE BLOCK READING

摘要

Disclosed is a semiconductor memory device with improved fuse sensing reliability in a slow power up operation. The semiconductor memory device includes: a memory cell array which includes a normal memory cell block and a spare memory cell block; and an anti-fuse block which stores fail address information related to defective memory cells in the normal memory cell block and senses the fail address information in response to a driving clock applied in a power up section. To reduce a fuse sensing speed in the slow power up operation, the semiconductor memory device further includes a fuse read circuit which detects the level of a driving voltage applied to the anti-fuse block in the power up section, generates a driving clock whose cycle is controlled according to the detected level, and reads the fail address information sensed in response to the driving clock from the anti-fuse block.