发明名称 Voltage generator of nonvolatile memory device
摘要 A voltage generator of a nonvolatile memory device includes a pump circuit for generating a pump output voltage by performing a pumping operation and raise or maintain the output voltage in response to a double enable signal or a single enable signal, a first regulator for comparing a first division voltage with a first reference voltage and generating the double enable signal according to a result of the comparison, a second regulator for comparing a second division voltage with a second reference voltage and outputting the voltage of the first level as a first regulation voltage, and a third regulator for comparing the second division voltage with the second reference voltage and generating the single enable signal according to a result of the comparison.
申请公布号 US8934307(B2) 申请公布日期 2015.01.13
申请号 US201213605947 申请日期 2012.09.06
申请人 SK Hynix Inc. 发明人 Chu Gyo Soo
分类号 G11C5/14 主分类号 G11C5/14
代理机构 IP & T Group LLP 代理人 IP & T Group LLP
主权项 1. A voltage generator of a nonvolatile memory device, comprising: an oscillator configured to generate clocks; a pump circuit configured to generate a pump output voltage in response to the clocks; a first regulator configured to compare a first division voltage, divided from the pump output voltage, with a first reference voltage in response to a pass regulator enable signal and generate a double enable signal for controlling the oscillator according to a result of the comparison; a second regulator comprising a comparator for comparing a second division voltage with a second reference voltage in response to a double regulator signal and generating a control signal according to a result of the comparison, a control circuit for supplying the pump output voltage to an output terminal in response to the control signal, and a voltage divider for generating the second division voltage by dividing voltage of the output terminal; and a third regulator configured to compare the second division voltage and a third reference voltage in response to a single regulator signal and generate a single enable signal for controlling the oscillator according to a result of the comparison, wherein the first regulator and the second regulator are activated when a double regulation operation is performed and the third regulator is activated when a single regulation operation is performed.
地址 Gyeonggi-do KR