Hybrid analog-to-digital converter having multiple ADC modes

摘要

A hybrid ADC having a successive approximation register (SAR) ADC mode for generating a bit of a digital signal and a ramp ADC mode for generating an additional bit of the digital signal is disclosed. When in the SAR ADC mode, a control circuit is configured to disable a ramp signal generator; disable a counter; and enable a register to control an offset stage to set the magnitude of an offset voltage that is provided to an input of a comparator of the ADC. When in the ramp ADC mode, the control circuit is configured to enable the ramp signal generator to provide a ramp signal to the input of the comparator; enable the counter to begin providing the digital count in response to the output of the comparator; and disable the register so that the offset stage is not providing the offset voltage.

主权项

1. A hybrid analog to digital converter (ADC) having a successive approximation register (SAR) ADC mode for generating at least one bit of a digital signal and a ramp ADC mode for generating at least one additional bit of the digital signal, the hybrid ADC comprising:
a sampling stage coupled to receive and sample an analog input; a comparator having a first input coupled to receive an output of the sampling stage and a second input coupled to receive a first reference voltage, wherein the first reference voltage is a black level voltage of at least one pixel of an image sensor; a ramp signal generator coupled to selectively provide a ramp signal to the first input of the comparator; an offset stage coupled to selectively provide a variable offset voltage to the first input of the comparator; a register coupled to control the offset stage to set a magnitude of the offset voltage in response to an output of the comparator; a counter coupled to the output of the comparator to provide a digital count when the ADC is in the ramp ADC mode; and a control circuit coupled to control the ramp signal generator and the register, wherein, when in the SAR ADC mode, the control circuit is configured to enable the register to control the offset stage to set the magnitude of the offset voltage in response to the output of the comparator; and when in the ramp ADC mode, the control circuit is configured to,
enable the ramp signal generator to provide the ramp signal to the first input of the comparator; andenable the counter to begin providing the digital count in response to the output of the comparator.