ERROR CORRECTION DECODER AND ERROR CORRECTION DECODING METHOD

摘要

According to one embodiment, an error correction decoder includes a storage unit and parity check circuit. The storage unit stores first reliability information corresponding to a hard decision result of each of a plurality of bits which form an ECC (Error Correction Code) frame defined by a parity check matrix, and second reliability information corresponding to a soft decision result of each of the plurality of bits. The storage unit includes a register configured to allow the parity check circuit to steadily read out at least the first reliability information. The parity check circuit executes parity checking of a temporary estimated word based on the first reliability information using the parity check matrix. The parity check circuit executes parity checking once or more before completion of row processing and column processing of the entire parity check matrix by a calculation circuit for each trial of iterative decoding.

主权项

1. An error correction decoder comprising:
a storage unit configured to store first reliability information corresponding to a hard decision result of each of a plurality of bits which form an ECC (Error Correction Code) frame defined by a parity check matrix, and second reliability information corresponding to a soft decision result of each of the plurality of bits; a calculation circuit configured to execute row processing and column processing using the first reliability information and the second reliability information; and a parity check circuit configured to execute parity checking of a temporary estimated word based on the first reliability information using the parity check matrix, and wherein the storage unit includes a register configured to allow the parity check circuit to steadily read out at least the first reliability information, and the parity check circuit executes the parity checking at least once before completion of row processing and column processing of the entire parity check matrix by the calculation circuit for each trial of iterative decoding.