Self-timed error correcting code evaluation system and method

摘要

Error correcting codes (ECCs) have been proposed to be used in high frequency memory devices to detect errors in signals transmitted between a memory controller and a memory device. For high frequency memory devices, ECCs have delay characteristics of greater than one clock cycle. When the delay exceeds one clock cycle but is much less than two clock cycles, an entire second clock cycle must be added. By calculating and comparing the ECC value in a static logic circuit and a dynamic logic circuit, the logic delay is substantially reduced. In addition, the ECC value may be calculated and compared using two sets of static logic gates, where the second static logic gate is clocked by a clock signal that is delayed relative to the clock signal of the first set of logic gates.

主权项

1. An apparatus, comprising:
an input configured to receive a command and a received error correcting code (ECC); a first logic circuit configured to generate a partial sum of terms from the command; a command decoder configured to generate a decoded command based on the command; ECC valid logic configured to provide the decoded command to a memory responsive to a valid signal; and a second logic circuit coupled to the first logic circuit and the ECC valid logic, the second logic circuit configured to generate an ECC based on the partial sum of terms, the second logic circuit further configured to provide the valid signal based on a comparison of the generated ECC and the received ECC, wherein the valid signal and the decoded command are provided to the ECC valid logic at different times.