Speculative read in a cache coherent microprocessor

摘要

A cache coherence manager, disposed in a multi-core microprocessor, includes a request unit, an intervention unit, a response unit and an interface unit. The request unit receives coherent requests and selectively issues speculative requests in response. The interface unit selectively forwards the speculative requests to a memory. The interface unit includes at least three tables. Each entry in the first table represents an index to the second table. Each entry in the second table represents an index to the third table. The entry in the first table is allocated when a response to an associated intervention message is stored in the first table but before the speculative request is received by the interface unit. The entry in the second table is allocated when the speculative request is stored in the interface unit. The entry in the third table is allocated when the speculative request is issued to the memory.

主权项

1. A microprocessor comprising:
a plurality of processing cores; and a cache coherence manager adapted to maintain coherence between the plurality of processing cores and minimize latency in performing coherent requests, said cache coherence manager comprising:
a request unit configured to receive a coherent request from a first one of the plurality of cores and to selectively issue a speculative request in response;an intervention unit configured to send an intervention message associated with the coherent request to the plurality of cores;a memory interface unit configured to receive the speculative request and to selectively forward the speculative request to a memory, wherein said memory interface unit comprises a first table operative to track information associated with requests issued to the memory, a second table operative to track information associated with speculative requests received by the memory interface unit, and a third table, wherein an entry in said first table represents an index to said second table and wherein an entry in said second table represents an index to said third table, and wherein an index to said first table is allocated before a response to the intervention message is stored in the first table and before the speculative request is received by the memory interface unit; anda response unit configured to supply data associated with the coherent request to the first one of the plurality of cores.