发明名称 |
Implementing DRAM command timing adjustments to alleviate DRAM failures |
摘要 |
A method, system and computer program product are provided for implementing command timing adjustments to alleviate Dynamic Random Access Memory (DRAM) failures in a computer system. A predefined DRAM failure is detected. Responsive to the detected failure, a set of timers is adjusted for controlling predetermined timings used to access the DRAM. Responsive to the failure being resolved by the adjusted set of timers, checking for a predetermined level of performance is performed. |
申请公布号 |
US8930776(B2) |
申请公布日期 |
2015.01.06 |
申请号 |
US201213598072 |
申请日期 |
2012.08.29 |
申请人 |
International Business Machines Corporation |
发明人 |
Cordero Edgar R.;Henderson Joab D.;Kumar Divya;Sabrowski Jeffrey A.;Saetow Anuwat |
分类号 |
G06F11/00 |
主分类号 |
G06F11/00 |
代理机构 |
|
代理人 |
Pennington Joan |
主权项 |
1. A method for implementing command timing adjustments to alleviate Dynamic Random Access Memory (DRAM) failures in a computer system comprising:
detecting a predefined DRAM failure; responsive to detecting the predefined DRAM failure, adjusting a set of timers for controlling predetermined timings used to access DRAM including selectively providing predetermined adjustment values from characterization or relaxed to include a set percentage of margin; and responsive to the predefined DRAM failure being resolved by the adjusted set of timers, checking for a predetermined level of performance. |
地址 |
Armonk NY US |