Master core discovering enabled cores in microprocessor comprising plural multi-core dies

摘要

A core configuration discovery method and corresponding microprocessor are provided that does not rely on off-core logic or queries by system BIOS. Reset microcode is provided in the microprocessor's cores. Upon reset, the microcode queries and/or receives from other cores configuration-revealing information and collects the configuration-revealing information to determine a composite core configuration for the microprocessor. The composite core configuration may reveal the number of enabled cores, identify the enabled cores, reveal a hierarchical coordination system of the multi-core processor, such as a nodal map of the cores for certain inter-core communication processes or restricted activities, identify various domains and domain masters within such a system, and/or identify resources, such as voltage sources, clock sources, and caches, shared by various domains of the microprocessor. The composite core configuration may be used for power state management, reconfiguration, and other purposes.

主权项

1. A microprocessor configured to communicate with system memory over a system bus, the microprocessor comprising:
a plurality of semiconductor dies, wherein each of the dies comprises a plurality of processing cores, wherein one of the plurality of processing cores of each of the dies is designated as the master core, wherein each of the master cores is configured to:
communicate with each of the other cores of its die over inter-core communication channels to determine the number of enabled cores of the die, in response to a reset of the microprocessor, andcommunicate with the master core of each of the other dies over inter-die communication channels to determine the number of enabled cores of the microprocessor, after determining the number of enabled cores of the die;wherein the inter-core and inter-die communication channels are external to the system bus.