发明名称 Array voltage regulating technique to enable data operations on large cross-point memory arrays with resistive memory elements
摘要 Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to preserve states of memory elements in association with data operations using variable access signal magnitudes for other memory elements, such as implemented in third dimensional memory technology. In some embodiments, a memory device can include a cross-point array with resistive memory elements. An access signal generator can modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. A tracking signal generator is configured to track the modified magnitude of the signal and to apply a tracking signal to other resistive memory elements associated with other subsets of bit lines, the tracking signal having a magnitude at a differential amount from the modified magnitude of the signal.
申请公布号 US8929126(B2) 申请公布日期 2015.01.06
申请号 US201314024946 申请日期 2013.09.12
申请人 Unity Semiconductor Corporation 发明人 Siau Chang Hua
分类号 G11C11/00;G11C13/00;G11C11/419;G11C8/08;G11C5/06 主分类号 G11C11/00
代理机构 Stolowitz Ford Cowger LLP 代理人 Stolowitz Ford Cowger LLP
主权项 1. A memory device, comprising: a cross-point array including discrete re-writable non volatile two-terminal resistive memory elements disposed between word lines and subsets of bit lines; an access signal generator configured to modify a magnitude of a signal to generate a modified magnitude for the signal to access a discrete re-writable nonvolatile two-terminal resistive memory element associated with a word line and first one of the subsets of bit lines; and a tracking signal generator configured to track the modified magnitude of the signal at a distance from the access signal generator and to apply a tracking signal to other discrete re-writable non-volatile two-terminal resistive memory elements associated with others of the subsets of bit lines, the tracking signal having a magnitude at a differential amount from the modified magnitude of the signal; and a line driver configured to float the others of the subsets of the bit lines during application of the tracking signal.
地址 Sunnyvale CA US