Integrated delayed clock for high speed isolated SPI communication

摘要

A system may include a plurality of isolators to transfer data signals across an isolation barrier, one of the signals including a clock signal. A delay circuit may be included to receive the clock signal and provide a delayed clock signal that lags the clock signal by an amount representing a delay across the isolation barrier. The delayed clock signal may be delayed by a round trip propagation delay over the isolation barrier. The delayed clock signal may be used as a reference to read data sent over the isolation barrier.

主权项

1. A system, comprising:
a plurality of isolators to transfer data signals across an isolation barrier, one of the signals including a clock signal; and a delay circuit receiving the clock signal from one of the plurality of isolators and providing a delayed clock signal that lags the clock signal by an amount compensating for a round-trip of data across the isolation barrier.