Semiconductor device, and method of manufacturing the same

摘要

The generation of a variation in properties of vertical transistors is restrained. A vertical MOS transistor is formed in a semiconductor substrate. A first interlayer dielectric film and a first source wiring are formed over the front surface of the substrate. The first source wiring is formed over the first interlayer dielectric film, and is overlapped with the vertical MOS transistor as viewed in plan. Contacts are buried in the first interlayer dielectric film. Through the contacts, an n-type source layer of vertical MOS transistor is coupled with the first source wiring. Openings are made in the first source wiring.

主权项

1. A semiconductor device comprising:
a semiconductor substrate having at least two surfaces opposite to each other; a vertical transistor that is formed in the semiconductor substrate, and that has a gate electrode and a source layer at one surface side of the two surface sides of the semiconductor substrate and has a drain layer at the other surface side of the semiconductor substrate; a first interlayer dielectric film formed over the one surface of the semiconductor substrate; a first source wiring that is formed over the first interlayer dielectric film and overlapped with the vertical transistor as the source wiring is viewed in plan, and that has plural openings; and a contact through which the first source wiring is coupled with the source layer of the vertical transistor, wherein the semiconductor substrate includes a power control region where the vertical transistor is formed and a logic region where a logic circuit is formed, the semiconductor device further comprising a planar MOS transistor formed in the logic region of the semiconductor substrate, and configured as the logic circuit, wherein the first interlayer dielectric film is formed in the logic region, the semiconductor device further comprising: a second interlayer dielectric film over the first interlayer dielectric film and the source wiring; a second source wiring formed over the second interlayer dielectric film and positioned in the power control region; a first via buried in the second interlayer dielectric film to couple the first source wiring and the second source wiring with each other; and a logic wiring formed over the second interlayer dielectric film and positioned in the logic region, the logic wiring being lower in planar density than the second source wiring.