TDI Imaging System With Variable Voltage Readout Clock Signals

摘要

A Time Delay and Integration (TDI) imaging system utilizing variable voltage readout clock signals having progressively increasing amplitudes defined as a function of pixel row location, where pixel rows positioned to receive/collect/transfer image-related charges at the start of the TDI imaging process are controlled using lower amplitude readout clock signals than pixel rows positioned to receive/collect/transfer image-related charges near the end of the TDI process. The clock signal amplitude for each pixel row is determined by the expected maximum amplitude needed to hold and transfer image charges by the pixels of that row. Multiple (e.g., three) primary phase signals are generated that are passed through splitters to provide multiple identical secondary phase signals, and then drivers having gain control circuitry are utilized to produce voltage readout clock signals having the same phases as the primary phase signals, but having two or more different voltage amplitudes.

主权项

1. A Time Delay and Integration (TDI) imaging system, comprising:
a sensor including an array of pixels arranged in a plurality of rows and a plurality of columns, phase signal generating means for generating a plurality of primary phase signals; means for splitting each of said plurality of primary phase signals into a plurality of secondary phase signals such that a first said primary phase signal is split into a plurality of identical first secondary phase signals, and a second said primary phase signal is split into a plurality of second secondary phase signals; a plurality of drivers for generating a plurality of readout clock signals in accordance with said plurality of secondary phase signals, said plurality of drivers being coupled to said sensor such that each row of said pixels receives at least two readout clock signals respectively generated by associated said drivers in accordance with associated secondary phase signals; and gain control means for controlling the plurality of drivers such that a first row of pixels disposed adjacent to a first end of said plurality of columns receives first and second readout clock signals having a first amplitude, and a second row of pixels disposed adjacent to a second end of said plurality of columns receives third and fourth readout clock signals having a second amplitude, wherein said second amplitude is greater than said first amplitude.