SYSTEM AND METHOD FOR CALIBRATING CHIPS IN A 3D CHIP STACK ARCHITECTURE

摘要

A system and method is disclosed for adaptively adjusting a driving strength of a signal between a first and second chip in a 3D architecture/stack. This may be used to adaptively calibrate a chip in a 3D architecture/stack. The system may include a transmission circuit on one chip and a receiver circuit on another chip. Alternatively, the system may include a transmission and receiver circuit on just one chip.

主权项

1. A system for calibrating a chip in a 3D chip stack, the system comprising:
a first and a second chip in said chip stack; said first chip comprising a calibration driver circuit, a receiver circuit, and a plurality of loop circuits, wherein each loop circuit in a subset of said plurality of loop circuits includes a load on said second chip; wherein said calibration driver circuit is configured to send a calibration signal to each of said plurality of loop circuits; wherein said receiver circuit is configured to receive from said loop circuits a plurality of respective loop signals, determine a driving signal based in part on said loop signals, and send said driving signal to said calibration driver circuit; and wherein said calibration driver circuit is configured to produce a modified calibration signal in response to said driving signal.