Nonvolatile memory and method with improved I/O interface

摘要

Each I/O channel between a controller and one or more memory dice of a memory device has a driver on one end and a receiver at the other end. The receiver is optionally terminated with a pseudo open-drain (“POD”) termination instead of the conventional center-tapped (“CTT”) termination to save energy. During a read operation, data is driven from the memory die to a POD terminated receiver circuit in the controller. With POD termination, the degradation in performance due to the more non-linear driver in the memory die, fabricated for example in the NAND technology processing, is alleviated by an adaptive reference voltage level adjustment in the receiver circuit of the controller. Optionally, the receiver circuit of a memory die is also provided with an adaptive reference level adjustment.

主权项

1. A non-volatile memory device, comprising:
an I/O channel for transporting data between first and second endpoints in the non-volatile memory device; a driver having a resistance (“Ron”) for driving data from the first endpoint through said I/O channel; and a receiver for receiving the data at the second endpoint through said I/O channel; said receiver further comprising: a termination circuit at the second endpoint having a pseudo open drain (POD) configuration with the second endpoint being shunt only by a first termination resistor (“Rtt”) to the supply voltage (“VDD”) such that a current flow in the I/O channel only when the data is driven by a transistor of said driver to ground; and a buffer circuit for buffering the data at the second endpoint, said buffer circuit being an operational amplifier for amplifying the data at the second endpoint relative to a reference voltage given by VDD/2 but adjusted by a predetermined ΔV, said ΔV being a function of a ratio, (Rtt/Ron) , between the resistance of the first termination resistor and the transistor of said driver.