Method and apparatus for efficiently implementing the advanced encryption standard

摘要

Implementations of Advanced Encryption Standard (AES) encryption and decryption processes are disclosed. In one embodiment of S-box processing, a block of 16 byte values is converted, each byte value being converted from a polynomial representation in GF(256) to a polynomial representation in GF((22)4). Multiplicative inverse polynomial representations in GF((22)4) are computed for each of the corresponding polynomial representations in GF((22)4). Finally corresponding multiplicative inverse polynomial representations in GF((22)4) are converted and an affine transformation is applied to generate corresponding polynomial representations in GF(256). In an alternative embodiment of S-box processing, powers of the polynomial representations are computed and multiplied together in GF(256) to generate multiplicative inverse polynomial representations in GF(256). In an embodiment of inverse-columns-mixing, the 16 byte values are converted from a polynomial representation in GF(256) to a polynomial representation in GF((24)2). A four-by-four matrix is applied to the transformed polynomial representation in GF((24)2) to implement the inverse-columns-mixing.

主权项

1. An apparatus comprising:
a first field conversion circuit to convert each of a plurality of 16 byte values of a block, respectively, from a first corresponding polynomial representation in GF(256) to a second corresponding polynomial representation in GF((22)4); a multiplicative inverse circuit to compute for each of the second corresponding polynomial representations in GF((22)4) of the 16 byte values, respectively, a corresponding multiplicative inverse polynomial representation in GF((22)4); and a second field conversion circuit to convert each corresponding multiplicative inverse polynomial representation in GF((22)4) and to apply an affine transformation by performing a multiplication of each corresponding multiplicative inverse polynomial representation with an 8-bit by 8-bit product matrix and a subsequent XOR with a constant byte value to generate, respectively, a third corresponding polynomial representation in GF(256) wherein the multiplication of each corresponding multiplicative inverse polynomial representation with an 8-bit by 8-bit product matrix and a subsequent XOR with a constant byte value is implemented by a series of XORs.