发明名称 USB video interface for ALPR cameras and associated method
摘要 A video processing system (10) for automatic license plate recognition (ALPR) provides an interface between video cameras (14, 16) and a host computer (20) through a single high speed USB connection (18). The system (10) supports four simultaneous composite video channels (28A, 28B, 28C, 28D) with two channels dedicated to an IR monochrome video and two channels dedicated to color video. Compression software incorporates a high speed memory for buffering and stripping unnecessary data from a digitized data stream. Monochrome channel data and color channel data are marked with an incrementing index to tag them with frame identification. As a result, processing software in the host computer can re-align the monochrome and color video information after processing a license plate image, regardless of the order of data arrival. Color overview and monochrome recognition images are provided at the same time, and thus show the same plate or vehicle.
申请公布号 US8922656(B2) 申请公布日期 2014.12.30
申请号 US201113636475 申请日期 2011.06.14
申请人 NDI Technologies, Inc. 发明人 Quinn Alan;Goonetilleke Tharaka
分类号 H04N7/18;G06K9/00;H04N5/77 主分类号 H04N7/18
代理机构 Allen, Dyer, Doppeit, Milbrath & Gilchrist 代理人 Allen, Dyer, Doppeit, Milbrath & Gilchrist
主权项 1. A video signal processing system (10) for receiving video feeds (12A, 12B, 12C, 12D) from automatic license plate recognition (ALPR) cameras (14, 16) and for providing a single USB connection (18) to a host computer (20), the system (10) comprising: video decoders (22A, 22B, 22C, 22D) adapted to accept video signal inputs (20) from the ALPR cameras (14, 16) and convert the video signal inputs (20) into digital component video formatted outputs (22) in video channels (28A, 28B, 28C, 28D); sync processor logic modules (30A, 30B, 30C, 30D) communicating with the video channels (28A, 28B, 28C, 28D), wherein input data provided thereby is clocked-in via each video decoder (22A, 22B, 22C, 22D) into a corresponding sync processor logic module (30A, 30B, 30C, 30D), and wherein the sync processor logic modules (30A, 30B, 30C, 30D) extract active video data from a data stream and discard non-active data unnecessary for ALPR applications; input FIFO modules (32A, 32B, 32C, 32D) for each of the video channels (32A, 32B, 32C, 32D), wherein each input FIFO module (32A, 32B, 32C, 32D) is controlled by one of the sync processor logic modules (30A, 30B, 30C, 30D) when the active video data is present; a memory controller (34) operable for receiving data from the input FIFO modules (32A, 32B, 32C, 32D); output FIFO modules (38A, 38B, 38C, 38D) operable for determining if there is sufficient available data storage and operable with the memory controller (34) for providing data for a particular video channel (28A, 28B, 28C, 28D); a compression module (36) receiving data from the memory controller (34) for each of the video channels (32A, 32B, 32C, 32D) and adaptable for storing software instruction for compressing the data sent to the output FIFO modules (38A, 38B, 38C, 38D) for each video channel (32A, 32B, 32C, 32D), wherein the memory controller (34) serves the output FIFO modules (38A, 38B, 38C, 38D) through the compression module (36); a FIFO control logic module (40) operable with each video channel (32A, 32B, 32C, 32D), the FIFO Control logic module (40) adapted to determine if the output FIFO modules (38A, 38B, 38C, 38D) have sufficient storage space for a preselected set of data entries, wherein the compression module (36) compresses the data and transmits resultant compressed data to the output FIFO modules (38A, 38B, 38C, 38D) via the FIFO control logic module (40); a USB transceiver (42) comprising a microcontroller, wherein the USB transceiver (42) is operable in a first in, first out (FIFO) mode for an initial configuration and setup of the FIFO output modules (38A, 38B, 38C, 38d); a USB endpoint controller (44) operable with the USB transceiver (42) for transferring data from the output FIFO modules (38A, 38B, 38C, 38D) to the USB Transceiver (42), wherein data from the Output FIFO modules (38A, 38B, 38C, 38D) is clocked in and clocked out using the USB transceiver (42) operable with the FIFO control logic module (40); and a single high speed USB connector (52) connected to the USB transceiver (42), the single high speed USB connector (52) thus providing the single USB connection (18) to the host computer (20).
地址 Winter Springs FL US