发明名称 METHOD OF DESIGNING POWER SUPPLY NETWORK
摘要 To design a power supply network of a 3D semiconductor device employing through-silicon-via (TSV) technology, board wiring of each of boards of the device is determined. An initial network structure is created for the boards. A layout of power bumps and through-silicon-vias, using the initial network structure, is produced such that voltages of all nodes of wiring of the boards are greater than a reference voltage. A semiconductor device having boards, power bumps and through-silicon-vias conforming to the layout is fabricated. Thus, the numbers of the through-silicon-vias and the power bumps of the power supply network of the semiconductor device are minimal
申请公布号 US2014380262(A1) 申请公布日期 2014.12.25
申请号 US201414308741 申请日期 2014.06.19
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 JANG MYUNG-SOO;LEE JAE-RIM;CHONG JONG-WHA;KIM JAE-HWAN;AHN BYUNG-GYU;JANG CHEOL-JON
分类号 G06F17/50;H05K3/00 主分类号 G06F17/50
代理机构 代理人
主权项 1. A method of manufacturing a semiconductor device having a plurality of boards stack one atop the other, wherein each board includes a substrate and wiring integrated with the substrate, and the wiring of each board has a plurality of nodes, the method comprising: determining board wiring for each of the boards; devising an initial network structure of the boards having the determined board wiring; using the initial network structure to compose a layout of a power supply network having power bumps disposed at respective nodes of the wiring of one of the boards, and through-silicon-vias connecting respective nodes of the wiring of the boards and satisfying a condition in which all of the nodes of the boards have voltages higher than a reference voltage when a voltage is impressed across the boards; and fabricating a semiconductor device of the board having the determined board wiring and power bumps and through-silicon vias conforming to said layout.
地址 SUWON-SI KR