Nearly buffer zone free layout methodology

摘要

The present disclosure relates to a layout arrangement and method to minimize the area overhead associated with a transition between a semiconductor device array and background features. A nearly buffer zone free layout methodology is proposed, wherein an array of square unit cells with a first pattern density value is surrounded by background features with a second pattern density value. A difference between the first pattern density value and second pattern density value results in a density gradient at an edge of the array. Unit cells on the edge of the array which are impacted by a shape tolerance stress resulting from the density gradient are identified and reconfigured from a square shape aspect ratio to a rectangular shape aspect ratio with along axis of the unit cell oriented in a direction parallel to the variation induced shape tolerance stress to alleviate the variation.

主权项

1. A layout method, comprising:
identifying an edge cell as a unit cell arranged along a border between an array of unit cells with a first pattern density value and background features with a second pattern density value; and changing a cell shape aspect ratio of the edge cell from approximately 1:1 to greater than 1:1 to reduce variation of unit cell features induced by a shape tolerance stress that results from a density gradient between the first pattern density value and second pattern density value, wherein a long axis of the edge cell is oriented in a direction perpendicular to the border and parallel to the shape tolerance stress.