发明名称 Inter-module voltage balance correcting circuit of a power storage system
摘要 Provided is an inter-module voltage balance correcting circuit of a power storage system including a plurality of storage modules connected in series, each of the storage modules including a plurality of storage cells connected in series. The inter-module voltage balance correcting circuit includes a resistance voltage dividing circuit (R1-R2) that equally divides a series voltage across a first storage module and a second storage module connected in series; and a pair of transistors that are turned ON/OFF complementarily based on a voltage (Vp1-Vp2) appearing between an intermediate connecting point (p2) between the storage modules M1, M2 in series and a voltage dividing point p1 of the resistance voltage dividing circuit, and a bypass discharge resistive element is selectively connected to modules by turning ON/OFF the complementary transistors.
申请公布号 US8917059(B2) 申请公布日期 2014.12.23
申请号 US200913003662 申请日期 2009.08.05
申请人 FDK Corporation 发明人 Nakao Fumiaki
分类号 H02J7/00;H01M10/44;H01M10/48;H01M10/42 主分类号 H02J7/00
代理机构 Harness, Dickey & Pierce, P.L.C. 代理人 Harness, Dickey & Pierce, P.L.C.
主权项 1. An inter-module voltage balance correcting circuit of a power storage system including a plurality of storage modules connected in series, each of the storage modules including a plurality of storage cells connected in series, the inter-module voltage balance correcting circuit comprising: a resistance voltage dividing circuit that equally divides a series voltage across a first storage module and a second storage module connected in series; a pair of transistors that are turned ON/OFF in a complementary manner based on a voltage that appears between an intermediate connecting point between the first and second storage modules and a voltage dividing point of the resistance voltage dividing circuit, the pair of transistors having commonly connected bases and commonly connected emitters; and a resistive element whose one end is connected to the commonly connected bases and whose other end is connected to the commonly connected emitters, the one end of the resistive element being further connected to the voltage dividing point, the other end of the resistive element being further connected to the intermediate connecting point, one of the pair of transistors being turned ON in a case where a dividing voltage that appears at the voltage dividing point becomes higher than an intermediate voltage that appears at the intermediate connecting point and causing a bypass discharge resistive element to be connected to a storage module situated at a positive side of the series-connected storage modules, the other of the pair of transistors being turned ON in a case where the dividing voltage becomes lower than the intermediate voltage and causing a bypass discharge resistive element to be connected to a storage module situated at a negative side of the series-connected storage modules.
地址 Tokyo JP
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