| 摘要 |
<p>A data processor has a pipeline for processing instructions. The output from a first instruction in the pipeline is used as an input to a second instruction in the pipeline. The processor replaces the second instruction with a combined instruction, which produces the same output as performing the two instructions in sequence. This output is independent of the execution of the first instruction. The first instruction may generate a base address for the second instruction. The second instruction may include an address offset. The combined base address and offset may be too long to fit in an architected instruction of the processor. The later instruction may be a load, store, arithmetic or logical operation. The first instruction may be executed if it has already issued or if another instruction depends on its result. Otherwise, it may be removed from the instruction stream.</p> |
