发明名称 PLL
摘要 One embodiment provides a phase-locked loop (PLL), in which a sequencer controls a loop filter such that, when a signal indicating turning-off of a power supply of the PLL is input thereto, or when a signal indicating turning-on of the power supply of the PLL is input thereto, a resistance value of a first resistance change device in the loop filter is a first resistance value, and that, after the PLL is stabilized, the resistance value of the first resistance change device is a second resistance value which is higher than the first resistance value.
申请公布号 JP5643725(B2) 申请公布日期 2014.12.17
申请号 JP20110166073 申请日期 2011.07.28
申请人 发明人
分类号 H03L7/107;H03K5/26;H03K17/06;H03K17/687;H03L7/093 主分类号 H03L7/107
代理机构 代理人
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