Mux-based digital delay interpolator

摘要

A digital delay interpolator may include an array of multiplexers, each multiplexer configured to be input with first and second input voltages, one of the first and second input voltages being delayed in respect to the other, and receive a respective selection signal. The digital delay interpolator may include output lines respectively coupled to the array of multiplexers, and an output terminal configured to be coupled in common to the output lines. Each multiplexer may be configured to selectively output on the respective output line one of the first and the second input voltages based upon a logic value of the respective selection signal.

主权项

1. A digital delay interpolator comprising:
at least one array of multiplexers, each multiplexer configured to
be input with first and second input voltages, one of the first and second input voltages being a delayed replica of the other input voltage, andreceive a respective selection signal; a plurality of output lines respectively coupled to said at least one array of multiplexers; and an output terminal configured to be coupled in common to said plurality of output lines and output a signal delayed by a time delay value based upon a total output capacitance of a number of multiplexers in said at least one array of multiplexers; each multiplexer of said at least one array thereof being configured to selectively output on the respective output line one of the first and the second input voltages based upon a logic value of the respective selection signal.