发明名称 Semiconductor integrated circuit
摘要 One embodiment provides a semiconductor integrated circuit, including: a first input wire; a second input wire; a first look-up table (LUT) comprising: a plurality of first memories; a first number of first switches connected to the first input wire; and a second number of second switches connected to the second input wire, the second number being less than the first number, the first LUT being configured to output information which is stored in one of the first memories; and a second LUT including: a plurality of second memories; a third number of third switches connected to the second input wire; and a fourth number of fourth switches connected to the first input wire, the fourth number being less than the third number, the second LUT being configured to output information which is stored in one of the second memories.
申请公布号 US8912822(B2) 申请公布日期 2014.12.16
申请号 US201313753091 申请日期 2013.01.29
申请人 Kabushiki Kaisha Toshiba 发明人 Yasuda Shinichi;Oda Masato;Fujita Shinobu
分类号 H03K19/177 主分类号 H03K19/177
代理机构 Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P. 代理人 Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
主权项 1. A semiconductor integrated circuit, comprising: a plurality of input wires comprising: a first input wire; and a second input wire; a first look-up table (LUT) comprising: a first memory group comprising a plurality of first memories;a first output terminal; anda first multiplexer comprising a first number of first switches connected to the first input wire and a second number of second switches connected to the second input wire, the second number being less than the first number, the first multiplexer being configured to transfer information from one of the first memories to the first output terminal according to signals input from the input wires; and a second LUT comprising: a second memory group comprising a plurality of second memories;a second output terminal; anda second multiplexer comprising a third number of third switches connected to the second input wire and a fourth number of fourth switches connected to the first input wire, the fourth number being less than the third number, the second multiplexer being configured to transfer information from one of the second memories to the second output terminal according to the signals input from the input wires.
地址 Tokyo JP