Dual-side interconnected CMOS for stacked integrated circuits

摘要

A stacked integrated circuit (IC) may be manufactured with a second tier wafer bonded to a double-sided first tier wafer. The double-sided first tier wafer includes back-end-of-line (BEOL) layers on a front and a back side of the wafer. Extended contacts within the first tier wafer connect the front side and the back side BEOL layers. The extended contact extends through a junction of the first tier wafer. The second tier wafer couples to the front side of the first tier wafer through the extended contacts. Additional contacts couple devices within the first tier wafer to the front side BEOL layers. When double-sided wafers are used in stacked ICs, the height of the stacked ICs may be reduced. The stacked ICs may include wafers of identical functions or wafers of different functions.

主权项

1. A method of manufacturing a stacked integrated circuit, comprising:
coupling a first back-end-of-line layer comprising a conductive layer to a contact point on a surface of a first tier by a via, the first back-end-of-line layer on a first side of the first tier and the contact on a second side of the first tier opposite the first side; and extending a first contact through a source region or a drain region in the first tier the first contact coupled between the conductive layer and the contact point and configured to provide an electrical path through the first tier.