REDUNDANCY EVALUATION CIRCUIT FOR SEMICONDUCTOR DEVICE

摘要

A redundancy evaluation circuit has (m+1) fuse boxes and a comparator, wherein the m fuse box output a fuse status address signal and the other one fuse box outputs a comparator enable signal. Each fuse box has a common stage circuit and k redundant cells. The k redundant cells shares the precharge transistor and an inverted latch of the common stage circuit, and the fuse in the selected redundant cell affects the output of the corresponding fuse box. The comparator enabled by the comparator enable signal compares the fuse status address signal and a defective element address signal to generate a redundancy enable signal. The redundancy evaluation circuit has a small layout area.

主权项

1. A redundancy evaluation circuit, comprising:
(m+1) fuse boxes, wherein m is a bit number of a defective element address signal, and each of the fuse boxes comprises: a common stage circuit, having a precharge transistor and an inverted latch, wherein the precharge transistor is controlled by a precharge signal to pull up a common node to a logic high level, and the inverted latch outputs an inversion of a level at the common node; and k redundant cells, each redundant cell has a transistor and a fuse, wherein a first and second ends of the transistor is connected to the common node and a low reference voltage through the fuse respectively, a gate of the transistor receive one of k selection signals, wherein k is a number of circuit blocks; and a comparator, enabled by a comparator enable signal, comparing a fuse status address signal and a defective element address signal to generate a redundancy enable signal, wherein the m fuse boxes output the m inversions of the m levels at the m common nodes thereof as the fuse status address signal, and the other one fuse box output the inversion of the level at the common node thereof as the comparator enable signal.