Single-poly floating-gate transistor comprising an erase gate formed in the substrate

摘要

An erasable programmable single-poly nonvolatile memory includes a substrate structure; a first PMOS transistor comprising a select gate (34), a first source/drain region (31), and a second source/drain region (32), wherein the select gate is connected to a select gate voltage, and the first source/drain region is connected to a source line voltage; a second PMOS transistor comprising the second source/drain region (32), a third source/drain region (33), and a floating gate (36), wherein the third source/drain region is connected to a bit line voltage and the first, second and third source/drain regions are constructed in an N-well region (NW); and an erase gate region (35) adjacent to the floating gate (36), wherein the erase gate region comprises an n-type source/drain region (38) connected to an erase line voltage and a P-well region (PW); wherein the N-well region (NW) and the P-well region (PW) are formed in the substrate structure.