发明名称 |
減少した転位パイルアップを有する半導体ヘテロ構造および関連した方法 |
摘要 |
Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein. |
申请公布号 |
JP5639248(B2) |
申请公布日期 |
2014.12.10 |
申请号 |
JP20130229066 |
申请日期 |
2013.11.05 |
申请人 |
台湾積體電路製造股▲ふん▼有限公司Taiwan Semiconductor Manufacturing Company,Ltd. |
发明人 |
クリストファー レイツ;クリストファー ビネイス;リチャード ウェストホフ;ビッキー ヤン;マシュー カリー |
分类号 |
H01L21/20;C30B25/02;C30B29/52;H01L21/205;H01L21/302;H01L21/336;H01L21/8238;H01L29/78;H01L31/0328 |
主分类号 |
H01L21/20 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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