Array architecture for reduced voltage, low power, single poly EEPROM

摘要

An Electrically Erasable Programmable Read Only Memory (EEPROM) memory array (FIG. 7) is disclosed. The memory array includes a plurality of memory cells arranged in rows and columns. Each memory cell has a switch (714), an access transistor (716), and a sense transistor (720). A current path of each access transistor is connected in series with a current path of each respective sense transistor. A first program data lead (706) is connected to the switch of each memory cell in a first column. A bit line (718) is connected to the current path of each access transistor in the first column. A read select lead (721) is connected to a control terminal of each access transistor in the first row. A first row select lead (700) is connected to a control terminal of the switch in each memory cell in a first row.

主权项

1. A memory array, comprising:
a plurality of nonvolatile memory cells arranged in rows and columns, each memory cell having a first switch, a second switch, an access transistor, and a sense transistor, wherein a current path of each access transistor is connected in series with a current path of each respective sense transistor; a bit line connected to the current path of each access transistor in a first column; a read select lead connected to a control terminal of each access transistor in a first row; a first program data lead connected to the first switch of each memory cell in the first column and coupled to receive one of a first and a second program voltage; a control gate capacitor coupled between the first switch and a control terminal of the sense transistor of each respective memory cell, wherein the control gate capacitor being formed on a first portion of a dielectric layer and the sense transistor being formed on a second portion of the dielectric layer; a first row select lead coupled to a control terminal of the first switch in each memory cell in the first row, wherein the first switch applies said one of a first and a second program voltage to the control gate capacitor in each respective memory cell in the first row in response to a signal on the first row select lead; a second program data lead coupled to the second switch of said each memory cell in the first column; and a second row select lead coupled to a control terminal of the second switch in said each respective memory cell in the first row.