发明名称 |
Apparatus and methods for converting analog signal to N-bit digital data |
摘要 |
An apparatus includes a sample holding circuit, a comparator, a digital-to-analog converter, a clock generator, a successive approximation logic circuit, and a background calibration circuit. The apparatus converts an analog signal into digital data based on an asynchronous clock signal. The clock signal follows the number of clocks in a converting operation section through a background calibration scheme. |
申请公布号 |
US8907834(B2) |
申请公布日期 |
2014.12.09 |
申请号 |
US201314101747 |
申请日期 |
2013.12.10 |
申请人 |
Samsung Electronics Co., Ltd. |
发明人 |
Lee Choong-Hoon;Choi Michael |
分类号 |
H03M1/38;H03M1/12;H03M1/00;H03M1/06 |
主分类号 |
H03M1/38 |
代理机构 |
F. Chau & Associates, LLC |
代理人 |
F. Chau & Associates, LLC |
主权项 |
1. An apparatus for converting an analog signal into multi-bit digital data, the apparatus comprising:
a sample holding circuit configured to sample and hold the analog signal; a comparator configured to compare the sampled and held analog signal with an analog reference signal in response to a clock signal; a digital-to-analog converter configured to convert the multi-bit digital data into the analog reference signal and provide the analog reference signal to the comparator; a clock generator configured to generate the clock signal in response to an operation state of the comparator and configured to control a period of the clock signal according to a delay time varied by a control signal; a successive approximation logic circuit configured to successively search for a binary signal that is approximated to an output signal of the comparator from a most significant bit to a least significant bit of the binary signal in response to the clock signal and configured to provide the multi-bit digital data resulting from the search to the digital-to-analog converter; and a background calibration circuit configured to sense a cycle number of the clock signal used in the comparator and the successive approximation logic circuit at a conversion completion time point and configured to generate the control signal such that a next cycle number of the clock signal to be used for a subsequent converting operation cycle follows an N-th clock cycle of the clock signal. |
地址 |
Suwon-Si, Gyeonggi-Do KR |