Stable SRAM cell

摘要

SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.

主权项

1. A method for accessing a SRAM cell in a SRAM cell array, the method comprising:
asserting a word line to select a row of a plurality of rows in the SRAM cell array, wherein the row corresponds to the SRAM cell; asserting a column select line to select a column of a plurality of columns in the SRAM cell array, wherein the column corresponds to the SRAM cell; and isolating other SRAM cells in the row by not asserting other column select lines corresponding to the other SRAM cells in the row.