发明名称 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
摘要 <p>PROBLEM TO BE SOLVED: To improve overlay accuracy in a main body pattern within a main body chip area in a lithography step.SOLUTION: Within a main body chip area of a mask MSKS of a processing layer which is exposed before a layer to be aligned, a CMP dummy area DAS is provided for disposing a plurality of CMP dummies DP therein and within a main body chip area of a mask MSKG to be used for exposing the layer to be aligned, a CMP dummy area DAG is provided in which an alignment mark AMG and the plurality of CMP dummies DP are disposed. The alignment mark AMG is disposed in an overlap area DAD extracted from the CMP dummy area DAS of the mask MSKS of the processing layer which is exposed before the layer to be aligned, and the CMP dummy area DAG of the mask MSKG of the layer to be aligned. In the mask MSKS of the processing layer which is exposed before the layer to be aligned, no CMP dummy DP is disposed at a position corresponding to the alignment mark AMG.</p>
申请公布号 JP2014229726(A) 申请公布日期 2014.12.08
申请号 JP20130107736 申请日期 2013.05.22
申请人 RENESAS ELECTRONICS CORP 发明人 HAGIWARA TAKUYA;TANAKA TOSHIHIKO;IMAI AKIRA
分类号 H01L21/027 主分类号 H01L21/027
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