发明名称 |
VOLTAGE REGULATOR |
摘要 |
Provided is a voltage regulator having satisfactory transient response characteristics. The voltage regulator includes: a first amplifier for detecting that undershoot occurs in an output voltage; a second amplifier for detecting that overshoot occurs in the output voltage; a first constant current circuit for increasing a bias current of an error amplifier circuit by a first amount for a first time period in response to a signal determined based on one of an output signal of the first amplifier and an output signal of the second amplifier; a second constant current circuit for increasing the bias current of the error amplifier circuit by a second amount larger than the first amount for a second time period shorter than the first time period in response to a signal determined based on the output signal of the first amplifier; and a first switch circuit for pulling up a gate of an output transistor in response to a signal determined based on the output signal of the second amplifier. |
申请公布号 |
US2014354249(A1) |
申请公布日期 |
2014.12.04 |
申请号 |
US201414287999 |
申请日期 |
2014.05.27 |
申请人 |
Seiko Instruments Inc. |
发明人 |
KUROZO Tadashi;YOKOYAMA Tomoyuki |
分类号 |
H02M1/08 |
主分类号 |
H02M1/08 |
代理机构 |
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代理人 |
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主权项 |
1. A voltage regulator, comprising:
an error amplifier circuit for amplifying a difference between a divided voltage obtained by dividing an output voltage output from an output transistor and a reference voltage, and for outputting the amplified difference to control a gate of the output transistor; a first amplifier for detecting that undershoot occurs in the output voltage; a second amplifier for detecting that overshoot occurs in the output voltage; a first constant current circuit for increasing a bias current of the error amplifier circuit by a first amount for a first time period in response to a signal determined based on one of an output signal of the first amplifier and an output signal of the second amplifier; a second constant current circuit for increasing the bias current of the error amplifier circuit by a second amount larger than the first amount for a second time period shorter than the first time period in response to a signal determined based on the output signal of the first amplifier; and a first switch circuit for pulling up the gate of the output transistor in response to a signal determined based on the output signal of the second amplifier. |
地址 |
Chiba-shi JP |