| 摘要 |
Disclosed is a shift register including stages for sequentially outputting output pulses including carry and scan pulses. Odd-numbered stages supply corresponding scan pulses to odd-numbered gate lines in a sequential manner, and even-numbered stages supply corresponding scan pulses to even-numbered gate lines in a sequential manner. Each stage includes a carry output unit for generating a carry pulse, based on a first discharge voltage and a clock pulse having a low-level voltage equal to the first discharge voltage, and supplying the carry pulse to at least one of upstream and downstream stages, and a scan output unit for generating a scan pulse, based on a second discharge voltage having a higher voltage than the first discharge voltage and the clock pulse, and supplying the scan pulse to a corresponding gate line. |
| 主权项 |
1. A shift register comprising:
a plurality of stages for sequentially outputting output pulses comprising carry pulses and scan pulses, the plurality of stages including odd-numbered stages and even-numbered stages, wherein the odd-numbered stages of the plurality of stages supply corresponding scan pulses to odd-numbered gate lines in a sequential manner, respectively, and the even-numbered stages of the plurality of stages supply corresponding scan pulses to even-numbered gate lines in a sequential manner, respectively; wherein each of the stages of the plurality of stages comprises:
a carry output unit for generating a carry pulse, based on a first discharge voltage and a clock pulse, the clock pulse having a low-level voltage equal to the first discharge voltage, and supplying the generated carry pulse to at least one of an upstream stage and a downstream stage of the plurality of stages, anda scan output unit for generating a scan pulse, based on a second discharge voltage having a higher voltage value than the first discharge voltage and the clock pulse, and supplying the generated scan pulse to a corresponding gate line. |
