METHODS AND SYSTEMS TO REDUCE LOCATION-BASED VARIATIONS IN SWITCHING CHARACTERISTICS OF 3D RERAM ARRAYS

摘要

Methods for reducing location-based variations in the switching characteristics of memory cells within a memory array are described. In some cases, the resistance of an embedded resistor within each memory cell may be set to reduce the overall variation in series resistances for the memory cells within a memory array. For example, embedded resistors associated with far-far bits may be set to a lower resistance than embedded resistors associated with near-near bits. An embedded resistor may comprise a layer of polysilicon within a memory cell. Selective ion implantation may be used to reduce the embedded resistor resistance for memory cells within a particular region of the memory array and to form two or more different sets of embedded resistors within the memory array.

主权项

1. A method for manufacturing a semiconductor memory, comprising:
forming a first control line layer; forming a memory element layer over the first control line layer; forming an embedded resistor layer over the first control line layer, the embedded resistor layer includes a first portion associated with a first set of embedded resistors within a first region of a memory array and a second portion associated with a second set of embedded resistors within a second region of the memory array; and performing a first doping process to the first portion subsequent to the forming an embedded resistor layer, the performing a first doping process causes the first set of embedded resistors to be less resistive than the second set of embedded resistors.