CRACK ARREST VIAS FOR IC DEVICES

摘要

An integrated circuit (IC) device (300) includes a substrate (305) having a top surface (304) including active circuitry (309) including a plurality of I/O nodes (308), and a plurality of die pads (302) coupled to the plurality of I/O nodes. A first dielectric layer (306) including first dielectric vias (312) is over the plurality of die pads. A redirect layer (RDL) (314) including a plurality of RDL capture pads (318) is coupled to the plurality of die pads over the first dielectric vias. A second dielectric layer (320) including second dielectric vias (322) is over the plurality of RDL capture pads. At least one of the second dielectric vias is a crack arrest via that has a via shape that includes an apex that faces away from a neutral stress point of the IC die and is oriented along a line from the neutral stress point to the crack arrest via to face in a range of ± 30 degrees from the line. Under bump metallization (UBM) pads (324) are coupled to the plurality of RDL capture pads over the second dielectric vias, and metal bonding connectors (326) are on the UBM pads.