发明名称 SIMULATION METHOD AND SIMULATION DEVICE FOR SEMICONDUCTOR DEVICE
摘要 <p>PROBLEM TO BE SOLVED: To provide a method and a device for simulating a current collapse phenomenon occurring in a transistor composed of a group-III nitride semiconductor, and to provide a parameter extraction method.SOLUTION: There is provided a simulation method for a semiconductor device. The semiconductor device comprises: a substrate; a first semiconductor layer formed on the substrate; a second semiconductor layer formed on the first semiconductor layer and having a forbidden band width larger than that of the first semiconductor layer; a first source electrode and a second source electrode formed on the second semiconductor layer separately from each other; a first gate electrode and a second gate electrode formed on the second semiconductor layer; and a protection film formed on the second semiconductor layer so that at least a part of each of the first source electrode, the second source electrode, the first gate electrode, and the second gate electrode, is exposed.</p>
申请公布号 JP2014225482(A) 申请公布日期 2014.12.04
申请号 JP20110199298 申请日期 2011.09.13
申请人 PANASONIC CORP 发明人 UENO HIROAKI;UEDA DAISUKE
分类号 H01L21/338;H01L21/82;H01L21/822;H01L27/04;H01L29/00;H01L29/778;H01L29/812 主分类号 H01L21/338
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