| 摘要 |
The present invention relates to a shift register capable of stabilizing the output of a stage. The present invention includes stages which receive at least one among clock pulses having a phase difference and sequentially output a scan pulse through the output terminal. The n^th stage (n is a natural number) includes a first clock transmission line which is controlled according to a voltage applied to a set node, and is connected between the output terminal of a corresponding stage and a first clock transmission line which transmits a first clock pulse; an inversion part which controls the voltage of a reset node to have a non-active state when a voltage applied to the set node is in an active state and controls the voltage of a reset node to have an active state when a voltage applied to the set node is in an non-active state, alternately; and a reset switching device which controls the voltage of the set node according to a voltage applied to the reset node. |
