Partitioning electronic circuits for simulation on multicore processors

摘要

A circuit is simulated by using distributed computing to obtain a real solution. The circuit may be an entire integrated circuit, portion of an integrated circuit, or a circuit block. A circuit simulation technique of the invention generates a system graph, finds a tree, and partitions the tree into two or more subtrees. The technique identifies global links and local links in the graph. Each subtree may be solved individually using distributed, parallel computing (e.g., using multiple processor cores or multiple processors). Using the results for the subtrees, the technique obtains a real solution, branch voltages and currents, for the circuit.

主权项

1. A method comprising:
providing a system graph of an electronic circuit comprising impedance components; identifying each branch of the system graph as at least one of a tree branch or a link, wherein the tree branches form a tree of the system graph; using a processor, partitioning the tree into at least a first subtree and a second subtree; and identifying links of the system graph as at least one of a global link or a local link, wherein a global link forms a path from a branch of the first subtree to a branch of the second subtree, the first subtree is formed by repeatedly adding branches of the tree to the first subtree when a number of branches in the first subtree is less than a predefined count and there are branches in the tree which have not yet been assigned to a subtree, the second subtree is formed by repeatedly adding branches of the tree, not already assigned to the first subtree, to the second subtree when a number of branches in the second subtree is less than the predefined count and there are branches in the tree which have not yet been assigned to a subtree, and a loop with the global link and branches of the first and second subtrees has a voltage drop of zero.