NEGATIVE EDGE FLIP-FLOP WITH DUAL-PORT SLAVE LATCH

摘要

In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. The clock signals CLK and CLKN and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CLK and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CLK, CLKN, RET, RETN, SS and SSN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

主权项

1. A flip-flop circuit comprising:
a first inverter configured to receive a data bit (D1) and output a binary logical compliment (D1N) of the data bit (D1); a master latch configured to receive the binary logical compliment (D1N), a clock signal CLK, a binary logical compliment signal (CLKN) of the clock signal (CLK), a retain control signal (RET) and the binary logical compliment signal (RETN) of the retain control signal (RET), wherein signals CLK, CLKN, RET and RETN determine when the binary logical value of the data bit (D1) is presented on the output (ML0) of the master latch and when the output (ML0) of the master latch is latched in the mater latch; a transfer gate wherein the transfer gate transfers data from the output (MLO) of the master latch to the output of the transfer gate when the clock signal CLK transitions from a high logical value to a logical low value; a slave latch configured to receive the output of the transfer gate, a second data bit (D2), the clock signal (CLK), the binary logical compliment signal (CLKN) of the clock signal (CLK), the retain control signal (RET), the binary logical compliment signal (RETN) of the retain control signal (RET), a slave control signal (SS) and the binary logical compliment signal (SSN) of the slave control signal (SS) wherein signals (CLK), (CLKN), (RET), (RETN), (SS) and (SSN) determine whether the output of the transfer gate or the second data bit (D2) is latched in the slave latch; wherein the output of the transfer gate is (QN).