发明名称 A METHOD AND APPARATUS FOR DRIVING HALF BRIDGE CONNECTED SEMICONDUCTOR POWER SWITCHES WITH A STABLE AND EXTREMELY SHORT INTERLOCK DELAY COMBINED WITH A SWITCHING TRANSITION SPEED INCREASE AND A DRIVING POWER CONSUMPTION REDUCTION
摘要 A driving circuit (1) for at least one voltage controlled power switch device comprises a driver signal generating circuit (4) configured to receive a pulsed signal, in particular a pulse width modulated, PWM, or a pulse density modulated signal, PDM, signal (A) and to generate a first driver signal in response to a rising edge of the PWM signal (A) and a second driver signal in response to a falling edge of the PWM signal (A). A trigger signal generating circuit adapted to generate trigger signals for said voltage controlled power switch device (PT). The trigger signal generating circuit (5) comprises a first driving transistor configured to be switched on by the first driver signal such that an on-voltage trigger signal is supplied to a control electrode of said power switch device (PT) and a second driving transistor configured to be switched on by the second driver signal such that an off-voltage trigger signal is supplied to the control electrode of said power switch device (PT). The driving circuit (1) comprises at least one energy buffer component (6) coupled between the trigger signal generating circuit (5) and the control electrode of said power switch device (PT). The energy buffer component (6) is adapted to store signal energy of the on-voltage trigger signal until a threshold voltage of said power switch device (PT) is reached and adapted to release the stored signal energy to said control electrode of said power switch device (PT) when said threshold voltage of said power switch device (PT) has been reached.
申请公布号 EP2805418(A2) 申请公布日期 2014.11.26
申请号 EP20130700344 申请日期 2013.01.17
申请人 ZAJC, FRANC 发明人 ZAJC, FRANC
分类号 H03K19/00;H02M3/00;H03K17/00 主分类号 H03K19/00
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