发明名称 Memory management for cache consistency
摘要 Methods and systems for maintaining cache consistency are described. A group of instructions is executed. The group of instructions can include multiple memory operations, and also includes an instruction that when executed causes a cache line to be accessed. In response to execution of that instruction, an indicator associated with the group of instructions is updated to indicate that the cache line has been accessed. The cache line is indicated as having been accessed until execution of the group of instructions is ended.
申请公布号 US8898395(B1) 申请公布日期 2014.11.25
申请号 US200812121531 申请日期 2008.05.15
申请人 发明人 Rozas Guillermo J.
分类号 G06F12/00;G06F12/08 主分类号 G06F12/00
代理机构 代理人
主权项 1. A method of managing memory in a computer system, said method comprising: setting a first bit of an indicator associated with a cache line in a cache memory if said cache line has been accessed in response to a processor executing an instruction in a first group of instructions; setting a second bit of said indicator while said first bit remains set if said cache line has also been accessed in response to said processor executing an instruction in a second group of instructions; executing a third group of instructions that causes said cache line to be accessed, wherein said third group of instructions is executed by an agent other than said processor, wherein said processing comprises rolling back said first group of instructions provided said first bit is set and rolling back said second group of instructions provided said second bit is set before allowing an instruction in said third group to access said cache line, and otherwise granting said access; and processing said first group and said second group of instructions according to a value of said indicator.
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